«a2», prima «appunti di informatica libera» e prima ancora «appunti linux» è il risultato di un lavoro di studio dell'informatica --ormai conclusosi-- che ha occupato gli anni dal 1997 al 2013 e che ha richiesto anche la produzione di strumenti tipografici adatti alla sua realizzazione, partendo da un formato SGML ad hoc che si è sviluppato assieme all'opera. A fianco del lavoro principale in italiano c'è stato anche uno studio relativo alla logica digitale, denominato «from the ground up», abbreviabile come «a3», scritto però in inglese.
Tutte le edizioni disponibili di questo lavoro sono conservate presso archive.org:
Il sito informaticalibera.net, indicato nell'edizione 2013.11.11 di «a2» e nell'edizione I-2013b di «a3», che avrebbero dovuto essere il punto di riferimento dell'opera, non è più disponibile. I file contrassegnati con la data di edizione 2013.11.11a e I-2013c sono stati ritoccati a mano, per togliere quel riferimento ora non più valido. Al suo posto appare l'indirizzo del profilo professionale, contenente anche tutti i riferimenti a questo lavoro (linkedin.com/in/appunti2).
From the ground up: table of context
Download the latest edition (20130819c) from Archive.org
Part i Logic circuits
1 Logic functions and logic gates
1.1 NOT
1.2 .not-inverter. or .buffer.
1.3 AND
1.4 OR
1.5 XOR
1.6 Logic networks
1.7 Operator precedence
1.8 Irrelevant values inside the truth table
1.9 Equivalence
1.10 Sum of products
1.11 Karnaugh maps
1.12 Logic gates and multiple lines
1.13 Electronic logic gates
1.14 HDL
2 Introduction to Verilog
2.1 Minimal notions
2.2 Hello world!
2.3 Compiler directives
2.4 Signal values
2.5 Literal constants
2.6 Data types
2.7 Ports
2.8 Parameters
2.9 Module declaration
2.10 Module instance
2.11 Fully qualified path names
2.12 Primitives
2.13 Expressions
2.14 Vector and array addressing
2.15 Strings
2.16 Functions
2.17 Netlist modules: combinational circuits
2.18 Behavioural modules
2.19 Procedural assignments
2.20 Blocking delays
2.21 Wait for a level event
2.22 Wait for an event expressions
2.23 Event variables
2.24 System tasks and functions
2.25 Control structures
2.26 Thread control
3 Combinational circuits
3.1 Decoder
3.2 Demultiplexer
3.3 Multiplexer
3.4 Multiplexer and demultiplexer with parallel I/O
3.5 Binary encoder
3.6 Priority encoder
3.7 Logic units
3.8 Shift and rotation
3.9 Addition
3.10 Subtraction
3.11 Addition and subtraction together
3.12 Carry lookahead
3.13 Increment and decrement
3.14 2's complement
3.15 Multiplication
3.16 Division
3.17 Magnitude comparator
4 Arithmetic-logic unit
4.1 Status flags
4.2 Size truncation
4.3 Sign inversion
4.4 Addition and subtraction
4.5 Shift and rotation
4.6 Magnitude comparison
4.7 Multiplication
4.8 Division
4.9 Logic unit
4.10 Joining all the modules together
4.11 Bit sliced ALU
5 Latch and flip-flop
5.1 Propagation delay
5.2 Truth tables
5.3 SR latch
5.4 Bounce-free switch
5.5 Gated SR latches
5.6 SR flip-flop
5.7 Time: setup/hold and recovery/removal
5.8 D latch and D flip-flop
5.9 T flip-flop
5.10 JK flip-flop
5.11 Troublesome JK flip-flops
6 Registers
6.1 Multiplexer
6.2 Simple data register
6.3 Shift register
6.4 Asynchronous counter with T flip-flop
6.5 Synchronous T flip-flop counters
6.6 Synchronous counters with D flip-flops
6.7 Synchronous counters with parallel load
7 Bus and control unit
7.1 Tri-state buffer
7.2 Hardcoded bus control unit
7.3 Microcode
8 TKGate 2 introduction and troubleshooting
8.1 Modules
8.2 Module library or cut and paste between files
8.3 Bit-size
8.4 Cut and paste troubles
8.5 File PostScript and EPS
8.6 Multiplexers, demultiplexers and encoders depiction
u1 Traditional logic integrated circuits
u1.1 Data distributors or demultiplexers
i1.1.1 74138 3-to-8 data distributor or demultiplexer
i1.1.2 74139 dual 2-to-4 data distributor or demultiplexer
i1.1.3 74154 4-to-16 data distributor or demultiplexer
i1.1.4 74238 3-to-8 data distributor or demultiplexer
u1.2 Data selectors or multiplexers
i1.2.1 74150 1-of-16 data selector or multiplexer
i1.2.2 74151 1-of-8 data selector or multiplexer
i1.2.3 74153 dual 1-of-4 data selector or multiplexer
i1.2.4 74157 quad 1-of-2 data selector or multiplexer
u1.3 Special circuits
i1.3.1 74148 8-to-3 priority encoder
u1.4 Arithmetic units
i1.4.1 7483 4-bit binary full-adder
i1.4.2 7485 4-bit magnitude comparator
i1.4.3 74181 .a. ALU
i1.4.4 74181 .b. ALU
i1.4.5 74182 carry lookahead generator
i1.4.6 74381 4-bit ALU
i1.4.7 74382 4-bit ALU
u2 References
Part ii Simple CPU
9 A simple 8-bit CPU: version *A*
9.1 Version *A1*: fetch and execution
9.2 Version *A2*: memory index
9.2.1 Loading instructions
9.2.2 Storing instructions
9.3 Version *A3*: general purpose registers
9.4 Version *A4*: ALU
9.4.1 Instruction *not*
9.4.2 Instruction *and*
9.4.3 Instruction *or*
9.4.4 Instruction *xor*
9.4.5 Instruction *lshl* and *lshr*
9.4.6 Instruction *ashl* and *ashr*
9.4.7 Instruction *rotl* and *rotr*
9.4.8 Instruction *add*
9.4.9 Instruction *sub*
9.5 Version *A5*: flags
9.5.1 Instruction *rotcl* and *rotcr*
9.5.2 Instruction *add.carry*
9.5.3 Instruction *sub.borrow*
9.6 Version *A6*: branching
9.7 Version *A7*: stack
9.7.1 Instruction *push* and *pop*
9.7.2 Instruction *call* and *return*
9.8 Version *A8*: I/O
9.8.1 Communication with asynchronous devices
9.8.2 I/O devices implementation
9.8.3 External appearance of the synchronous interfaces
9.8.4 Synchronous keyboard interface
9.8.5 Synchronous display interface
9.8.6 The CPU data bus with the I/O interfaces
9.8.7 Instruction *out*
9.8.8 Instruction *in*
10 Version *B*: optimization
10.1 Uniform registers
10.2 Module *RAM*
10.3 Module *SEL*
10.4 Module *ALU*
10.5 Module *TTY*: the terminal
10.6 Module *CTRL*: control unit
10.7 Memories, fields, arguments and opcodes
10.8 Microcode
10.9 Macrocode: routine call
10.10 Macrocode: keyboard input and screen output
10.11 Version *B2*
11 Version *C*: 16-bit little-endian
11.1 General purpose 16-bit registers
11.2 Module *BUS*
11.3 Module *ALU*
11.4 Module *SEL*
11.5 Module *RAM*
11.6 Module *IRQ*
11.7 Module *IVT*
11.8 Module *CTRL*
11.9 Opcodes
11.10 Microcode
11.11 Interrupts management
11.12 Module *RTC*: real time clock
11.13 Module *TTY*
11.14 Module *HDD*
11.15 Macrocode: terminal usage example, through interrupts
12 Version *D*
12.1 General purpose registers
12.1.1 Module *RANK*
12.1.2 Modules *D.select* and *Q.select*
12.2 Module *VRn*
12.3 Module *RAM*
12.4 Module *ALU* and related submodules
12.5 Module *BUS*
12.6 Module *IRQ*
12.7 Modules *Dn*
12.8 Module *IVT*
12.8.1 Module *DRn*
12.9 Module *RTC*: real time clock
12.10 Module *TTY*
12.11 Module *HDD*
12.12 Module *CTRL*
12.12.1 Modules *Fn*
12.12.2 Module *CLK.CLR*
12.13 Memory and microcode fields
12.14 Opcodes
12.15 Microcode
12.16 Macrocode
13 Version *E*
13.1 General purpose modules
13.2 Module *MEM*
13.2.1 Module *MAR*
13.2.2 Module *MIR*
13.2.3 Module *MDR*
13.3 General purpose registers
13.4 Module *ALU* and related submodules
13.5 Module *BUS*
13.6 Module *IRQ*
13.7 Module *IVT*
13.8 Module *RTC*: real time clock
13.9 Module *TTY*
13.10 Module *HDD*
13.11 Module *CTRL*
13.11.1 Modules *Fn*
13.11.2 Module *CLK.CLR*
13.12 Memory and microcode fields
13.13 Opcodes
13.14 Microcode
13.15 Macrocode
14 Version *F*: 32-bit registers, big-endian, privileges
14.1 General purpose modules
14.2 Addition modules
14.3 Multiple clock lines
14.4 Bus
14.5 Registers: simple and with post-increment
14.6 Memory segmentation
14.7 Module *DA*
14.8 Module *CA*
14.9 Modules *M* and *RAM*
14.10 Module *IR*
14.11 Module *MD*
14.12 Module *IRQ*
14.13 Module *IVT*
14.14 Module *ALU*
14.15 Module *FL*
14.16 Module *TTY*
14.17 Module *HDD*
14.18 Module *CTRL*
14.19 Memory and microcode fields
14.20 Opcodes
14.21 Data initialization
14.22 Microcode
14.23 Process mode and interrupts
14.24 Macrocode example: .memcpy.
14.25 Macrocode example: TTY with interrupt
14.26 Macrocode example: user and supervisor
u3 References
«a2», ex «appunti di informatica libera»: indice dei contenuti
Scarica l'ultima edizione (20131111a) da Archive.org
Volume I Sistemi GNU/Linux
Volume II Scrittura e pubblicazione
Volume III Programmazione
Volume IV os32
Volume V Didattica in laboratorio
Volume VI ''a0''